1. Field
The present invention relates generally to data communications, and in particular serial point-to-point data communications.
2. Background Art
The speed of computers has dramatically increased over recent years. A considerable portion of that increase has resulted from the increased CPU speeds. However, computer speed also depends upon the speed of data communications, i.e., the ability for CPUs to communicate data to and from peripheral devices. For some time, the peripheral component interconnect (PCI) bus provided adequate peripheral connectivity. However, with increased CPU speeds and greater data transfer demands, the PCI bus quickly became the slowest link between CPU and peripheral. In particular, the PCI bus imposed substantial pin, power and clocking disadvantages in order to meet the increased data transfer requirements.
In response to these disadvantages, the PCI Express industry standard developed. The PCI Express industry standard adopted a serial protocol that uses low voltage differential signals, does not impose the same clocking disadvantages, and delivers higher bandwidth with reduced pin count. PCI Express offers up to 32 data channels (known as lanes) that provide serial point-to-point connectivity between a “root” device and an “endpoint” device.
The PCI Express protocol is a layered protocol, with the layers including a transaction layer, a data link layer, and a physical layer. The fundamental building block of communication between PCI Express-compliant devices is the transaction layer packet (TLP). The TLP contains a header, a data payload and an error correction segment (called a digest). One or more TLPs create a transaction that enables an operation in a PCI Express-complaint device. For example TLP transactions facilitate memory read and write operations.
As noted above, the PCI Express protocol was developed to offer a flexible high speed approach to the modern data communication device-to-device challenges. Nevertheless, with the ever increasing demand for efficient data transfer to service high performance computer designs, the efficiency of data transfer remains a high priority. Thus, there is an on-going need for enhancements to the PCI Express protocol. Any improvements to the PCI Express protocol must necessarily be backwards compatible with the standard PCI Express specifications.
As a consequence, device modifications are necessary to permit additional functionality from PCI Express protocol enhancements to be realized. Enhancements to the PCI Express protocol can be realized by upgrades to software drivers associated with the devices at either end of the communications link. Such upgraded software drivers program the memory-mapped space so that the associated devices can capitalize on the PCI Express protocol enhancements. Although upgrades to device software drivers are the preferred solution, very often such upgrades are not available in a timely fashion. Moreover, a PCI Express function is not permitted to access resources (e.g., configuration space) that are not owned by that function. While some limited access of foreign resources in a PCI Express environment may be possible using a peer-to-peer approach, many platforms do not support peer-to-peer access, and very few platforms support “read access” using a peer-to-peer approach. In addition, downstream PCI Express ports do not accept access to configuration space. Further, some systems block peer-to-peer access altogether via “Access Control Services.”
Therefore, there is a need for a method and system to implement PCI Express protocol enhancements in the absence of upgrades to associated device software drivers.